Silicon carbide (SiC) has a wider band gap and a higher dielectric breakdown voltage than silicon (Si), and therefore, is expected to be the best semiconductor material to make a next-generation low-loss power device. SiC has a lot of poly-types including cubic ones such as 3C—SiC and hexagonal ones such as 6H—SiC and 4H—SiC. Among these various poly-types, the one that is used generally to make a practical silicon carbide semiconductor element is 4H—SiC.
A metal-insulator-semiconductor field-effect transistor (MISFET) is a typical semiconductor element among various power elements that use SiC (see Patent Document No. 1, for example). In this description, a MISFET of SiC will sometimes be simply referred to herein as a “SiC-FET”. And a metal-oxide-semiconductor field-effect transistor (MOSFET) is one of those MISFETs.
FIG. 18 is a cross-sectional view illustrating a traditional trench type semiconductor element (SiC-FET) 1000. The semiconductor element 1000 includes a plurality of unit cells 1000u. The semiconductor element 1000 is made of a silicon carbide (SiC) semiconductor and has a structure in which an n−-drift layer 1020 is stacked on an n+-substrate (SiC substrate) 1010. A p-body region 1030 has been defined over the n−-drift layer 1020. A p+-body contact region 1050 and an n+-source region 1040 have been defined on the p-body region 1030. And a source electrode 1090 has been formed on the p+-body contact region 1050 and the n+-source region 1040. The semiconductor element 1000 has a trench 1020t, which may have a groove shape that runs through the source region 1040 and the p-body region 1030 to reach the drift layer 1020. On the sidewall of that trench 1020t, an n−-channel layer 1060 which connects together the n+-source region 1040 and the drift layer 1040 has been grown epitaxially. Further formed on the drift layer 1020 at the bottom of the trench 1020t, the n+-source region 1040, and the channel layer 1060 are a gate insulating film 1070 and a gate electrode 1080. Meanwhile, a drain electrode 1100 has been formed on the back surface of the n+-substrate 1010.
The source electrode 1090 is connected in parallel to the respective source electrodes of other cells with an upper interconnect electrode 1120. This upper interconnect electrode 1120 and the gate electrodes 1080 are electrically insulated from each other by an interlevel dielectric film 1110. The interlevel dielectric film 1110 has a plurality of holes 1110c, at which the upper interconnect electrode 1120 contacts with the source electrodes 1090. A lower interconnect electrode 1130 is arranged on the drain electrode 1100. By bonding the lower interconnect electrode 1130 with solder during a mounting process, this semiconductor element 1000 is fixed onto a leadframe or a module.
It was reported that when an epitaxial growth process was carried out on an SiC substrate through which trenches had been formed, the epitaxial film had different thicknesses on two opposing side surfaces of each of those trenches (see Non-Patent Document No. 1). If those side surfaces of a trench are perpendicular to the off-axis angle direction of the SiC substrate, then facets are formed around a shoulder portion on one side of the trench. In this case, the facets are (0001) planes that are basal planes of the SiC substrate. To the sidewall surface of the trench that is closer to those facets, a source gas that has not contributed to growth at those facets is supplied. They believe that the epitaxial film comes to have an increased thickness in this manner at the trench sidewall surface closer to those facets.